Intel Xeon Phi 'Knights Hill' Will Debut on the 10nm Process - 2nd Generation Omni-Path and HMC

So something, really interesting came up. Intel has started talking in hostage about its 10nm node and ane of the more solid roadmaps is already out. Xeon Phi is bluish's race horse in the HPC sector, where it is competing with strong GPGPU rivals, such as Nvidia, to go a share of the number crunching pie. Intel's Co-Processors tin can do everything a professional GPU can (and more) with one disquisitional advantage: they don't demand a CPU to drive them.

Slide Credit URL - Anandtech.com

Intel's 10nm, 3rd Generation, Knight's Hill Co-Processors to update Xeon Phi lineup in 2022+

Nvidia has recently unveiled the Tesla K80 which features the GK210 GPU (something we told you lot about a very long time ago) and I believe Intel was compelled by this annunciation that it announced its HPC plans. Knight's Loma constitutes the third iteration in the Xeon Phi family unit and is preceded by Knights Landing and Knights Corner. Interestingly, Knight'southward Corner just featured the GPU form gene, which Intel adopted considering of its user-friendly blueprint simply was something that had a big footprint. Knight'south Landing innovated into the familiar Socket (CPU) Packaging and offered businesses the option to choose whichever design they preferred.

From early on reports, Intel was planning on abandoning the GPU course factor completely but I am non certain how authentic that is anymore. From what the slide is implying, I look both form factors to stick around in the future. Keep in mind, withal, that Knight's Landing isn't available still (to my knowledge). Almost of the lineup is expected to land former in 2022, but as is the case with the HPC sector, concrete roadmaps are provided in advance for investors and bushiness to make critical decisions. Also, unlike the mainstream sector, any delay in a roadmap could cost Intel a lot of money, and then I expect the roadmap volition hold true to the letter.

Lets talk a scrap most Knight's Landing. It was congenital on the 14nm Process and used a modified silvermont core (x86 ofcourse). Information technology is besides one of the offset mass produced components that feature stacked DRAM. Since the GPU form cistron is usually limited (to heck) by the PCI-E lane, the CPU grade factor provides super-low latency and almost no bottlenecks. The on-packed stacked DRAM will come in a whooping 16 GB while there are connections for additional DDR42400Mhz retentivity.  That is a massive massive corporeality of memory to take onboard. However there is a technical grab (annotation the keyword technical). The HMC will not really be placed or stacked upon the die.

Intel will actually be surrounding the Xeon Phi die using a Micron-Intel custom made, super-loftier bandwidth, parallel path interface that will make the HMC announced as if its on the die. Infact it will act more or less like an L3 cache worth 16GB. You tin can await this size to increase with Knight's Hill. Ofcourse if you strip abroad the marketing material you lot would realize that an L3 cache is faster than the currently known speeds of HMC (depending on which processor you have). The Hybrid Memory Cube used in the Knights Landing Xeon Phi packet will feature upto 2000 TSVs and an ASIC at the base of the HMC to manage the DRAM package. It promises more than 5 times the bandwidth of DDR4 RAM and more than than xv times the bandwidth of DDR3 Ram. Because Intel is using a customized Micron 16GB HMC solution (they already have 2GB and 4GB variants) and a customized interface the bandwidth will exist 500GB/s. The Omnit-Path Interconnect can provide line speeds of upto 100Gbps.

The Xeon Phi platform is currently pretty much in its infancy and scaling between generations very GPU-like. Based on the projections and then far I would wait the new 10nm Knight's Hill Co-Processors to have functioning easily upwardly of 5 TFlOPS. I expect rival GPUs in 2022 to easily beat this number, but the inherent disadvantage of the PCI-Eastward Clogging and the compulsory CPU dependency makes Xeon Phi a very very viable culling for a supercomputing cluster.

Source: https://wccftech.com/intel-xeon-phi-knights-hill-debut-10nm-process/

Posted by: martineznevard.blogspot.com

Share this post